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C1 fil_out1 vss 10n ;
R3 fil_out1 fil_out 100K ; PB3 port = OC1 (output compare)
C2 fil_out vss 10n ;
.plot v(PD4) v(PD5) v(fil_out) v(fil_out1); Dispay in SCOPE
Ɏɚɣɥ Lab3.asm
;*************************************************************
;* PWM based sinewave generator, table based
;*************************************************************
.include "m16def.inc"
; Registers definitions
;
.def tmp = r16
.def angle = r17 ; Index to hold the sine phase angle (0 to 127)
;*************************************************************
; Reset and interrupt vectors handlers
;
.cseg
.org $00
reset_hnd:
rjmp start ;
.org OVF1addr
tim1_hnd:
rjmp tim1_ovf
;***************************************************************
; Timer 1 interrupt handler
;
tim1_ovf:
inc angle
andi angle, $7F ; truncates to 7 bits (0 – 127)
ldi ZL,low(sine_tbl*2) ; Get the table address and
ldi ZH,high(sine_tbl*2) ; add the angle phase. Result
add ZL,angle ; will be in R0 after calling 'lpm'
clr tmp ; lpm uses 16 bits index (Z)
adc ZH, tmp ; Z index is the pointer to the
lpm ; sine_tbl value for the angle phase
clr tmp
out OCR1AH, tmp ; Reload Timer 1 compare value.
50
out OCR1AL,R0 ; Necessary to reload both registers
reti
;************************************************************
; Reset handler. Initalizes port and Timer 1, and stay in a endless loop
;
start:
sbi DDRD, PD4 ; Set pin PD5 as output (is OC1 pin)
sbi DDRD, PD5
ldi tmp, high(RAMEND) ; ɢɧɢɰɢɚɥɢɡɚɰɢɹ ɩɚɦɹɬɢ ɫɬɟɤɚ
out SPH, tmp
ldi tmp, low(RAMEND)
out SPL, tmp ; ɡɚɜɟɪɲɟɧɢɟ ɢɧɢɰɢɚɥɢɡɚɰɢɢ ɩɚɦɹɬɢ ɫɬɟɤɚ
ldi tmp,(1<<TOIE1)
out TIMSK,tmp ; Enable Timer1_ovf interrupt
ldi tmp,(1<<PWM10)+(1<<COM1A1) ; Set Timer 1 in PWM mode
out TCCR1A,tmp ; 8 bit PWM not reverse (Fck/510)
ldi tmp,(1<<CS10)
out TCCR1B,tmp ; prescaler = 1
clr angle ; Start with phase = 0
sei ; Enable interrupts
main:
nop
nop
rjmp main ; Infinite loop: Timer1 interrupt will handle all
;*************************** SINE TABLE
***************************************
; Samples table : one period sampled on 128 samples and
; quantized on 7 bit
;
sine_tbl:
.db 0,0
.db 1,1
.db 2,3
.db 4,6
.db 7,9
.db 10,12
.db 14,16
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