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ɉɪɢɥɨɠɟɧɢɟ 4. ɋɢɫɬɟɦɚ ɤɨɦɚɧɞ ɦɢɤɪɨɤɨɧɬɪɨɥɥɟɪɚ ȺɌmɟgɚ16
ɢ ɞɢɪɟɤɬɢɜɵ ɹɡɵɤɚ Assembler
Ʉɨɦɚɧɞɵ ɩɟɪɟɫɵɥɤɢ AVR–ɦɢɤɪɨɤɨɧɬɪɨɥɥɟɪɨɜ
Ɇɧɟɦɨ-
ɧɢɤɚ
Ɉɩɪɚɧɞɵ Ɉɩɢɫɚɧɢɟ ɢɧɫɬɪɭɤɰɢɢ
ȼɵɩɨɥɧɹɟɦɚɹ
ɨɩɟɪɚɰɢɹ
Ɏɥɚ-
ɝɢ
Ɍɚɤɬɵ
mov Rd, Rr Move Between Re
g
isters Rd<– Rr None 1
mov Rd
,
Rr Co
py
Re
g
ister Word Rd+1:Rd<– Rr+1:Rr None 1
ldi Rd*
,
K Load Immediate Rd<– K None 1
ld Rd, X Load Indirect Rd<–
(
X
)
None 2
ld Rd
,
X+ Load Indirect and Post–Inc. Rd <–
(
X
),
X <– X + 1 None 2
ld Rd
,
–X Load Indirect and Pre–Dec. X<–X–1
,
Rd<–
(
X
)
None 2
ld Rd
,
Y Load Indirect Rd <–
(
Y
)
None 2
ld Rd
,
Y+ Load Indirect and Post–Inc. Rd <–
(
Y
),
Y <– Y + 1 None 2
ld Rd
,
–Y Load Indirect and Pre–Dec. Y<–Y–1
,
Rd<–
(
Y
)
None 2
ldd Rd, Y+q Load Indirect with Displace-
ment
Rd<– (Y + q) None 2
ld Rd
,
Z Load Indirect Rd<–
(
Z
)
None 2
ld Rd
,
Z+ Load Indirect and Post–Inc. Rd <–
(
Z
),
Z <– Z+1 None 2
ld Rd
,
–Z Load Indirect and Pre–Dec Z<– Z–1
,
Rd<–
(
Z
)
None 2
ldd Rd, Z+q Load Indirect
with Displacement
Rd<– (Z + q) None 2
lds Rd
,
k Load Direct from SRAM Rd<–
(
k
)
None 2
st X
,
Rr Store Indirect
(
X
)
<– Rr None 2
st X+
,
Rr Store Indirect and Post–Inc.
(
X
)
<– Rr
,
X <– X + 1 None 2
st –X
,
Rr Store Indirect and Pre–Dec. X<– X–1
,(
X
)
<– Rr None 2
st Y
,
Rr Store Indirect
(
Y
)
<– Rr None 2
st Y+
,
Rr Store Indirect and Post–Inc.
(
Y
)
<– Rr
,
Y <– Y + 1 None 2
st –Y
,
Rr Store Indirect and Pre–Dec. Y<– Y–1
,(
Y
)
<– Rr None 2
std Y+q, Rr Store Indirect withDisplace-
ment
(Y + q)<– Rr None 2
st Z
,
Rr Store Indirect
(
Z
)
<– Rr None 2
st Z+
,
Rr Store Indirect and Post–Inc.
(
Z
)
<– Rr
,
Z <– Z + 1 None 2
st –Z, Rr Store Indirect and Pre–Dec Z<– Z–1,(Z)<– Rr None 2
std Z+q,Rr Store Indirect with
Displacement
(Z + q)<– Rr None 2
sts k
,
Rr Store Direct to SRAM
(
k
)
<– Rr None 2
l
p
m Load Pro
g
ram Memor
y
R0<–
(
Z
)
None 3
lpm Rd, Z Load Program Memory Rd<–Z) None 3
lpm Rd, Z+ Load PrMem and Post–Inc. Rd <– (Z), Z=Z+1 None 3
s
p
m Store Pro
g
ram Memor
y
(
Z
)
<– R1:R0 None –
in Rd, P In Port Rd<– P None 1
out P, Rr Out Port P<– Rr None 1
push Rr Push Register on Stack STACK <– Rr;
SP<– SP–1
None 2
pop Rd Pop Register from Stack SP <– SP+1,
Rd <–STACK
None 2
94
Ⱥɪɢɮɦɟɬɢɱɟɫɤɢɟ ɢ ɥɨɝɢɱɟɫɤɢɟ ɤɨɦɚɧɞɵ ɦɢɤɪɨɤɨɧɬɪɨɥɥɟɪɚ ATmega163
Ɇɧɟɦ. Ɉɩɟɪ–ɞɵ Ɉɩɢɫɚɧɢɟ Ɉɩɟɪɚɰɢɹ Ɏɥɚɝɢ Ɍɚɤ
add Rd, Rr Add without Carry two Registers Rd <– Rd + Rr Z,C,N,V,H 1
adc Rd, Rr Add with Carry two Registers Rd<– Rd + Rr+ C Z,C,N,V 1
adiw Rdl, K ADD Immediate from Word Rdh:Rdl <–
Rdh:Rdl+K
Z,C,N,V,S 2
sub Rd, Rr Subtract without Carry two Registers Rd<– Rd–Rr Z,C,N,V,H 1
subi Rd*, K Subtract Constant from Register Rd<– Rd–K Z,C,N,V,H 1
sbc Rd, Rr Subtract with Carry two Registers Rd<– Rd–Rr–C Z,C,N,V,H 1
sbci Rd*, K Subtract with Carry Constant from
Register
Rd<– Rd–K–C Z,C,N,V,H 1
sbiw Rdl, K Subtract Immediate from Word Rdh:Rd <–
Rdh:Rdl– K
Z,C,N,V,S 2
and Rd, Rr Logical AND Registers Rd <– Rd Rr Z,N,V 1
andi Rd*, K Logical AND Register and Constant Rd <– Rd K Z,N,V 1
or Rd, Rr Logical OR Registers Rd <– Rd v Rr Z,N,V 1
ori Rd*, K Logical OR Register and Constant Rd<– RdvK Z,N,V 1
eor Rd, Rr Exclusive OR Registers Rd <– Rd Rr Z,N,V 1
com Rd One's Complement Rd <– $FF – Rd Z,C,N,V 1
neg Rd Two's Complement Rd<– $00–Rd Z,C,N,V 1
sbr Rd*, K Set Bit(s) in Register Rd<– RdvK Z,N,V 1
ser Rd Set Register Rd <– $FF None 1
cbr Rd*, K Clear Bit(s) in Register Rd<–Rd ($FF–K) Z,N,V 1
clr Rd Clear Register Rd <– $00 Z,N,V 1
inc Rd Increment Rd <– Rd + 1 Z,N,V 1
dec Rd Decrement Rd<– Rd–1 Z,N,V 1
tst Rd Test for Zero or Minus Rd <– Rd Rd Z
,
N
,
V 1
ɫɪ Rd, Rr Compare Rd–Rr Z, N,V,C,H 1
ɫ
ɪ
ɫ Rd
,
Rr Com
p
are with Carr
y
Rd–Rr–C Z
,
N
,
V
,
C
,
H 1
cpi Rd*, K Compare Re
g
ister with Immediate Rd–K Z, N,V,C,H 1
mul Rd, Rr Multiply Unsigned R1:R0<–RdxRr Z,C 2
muls Rd, Rr Multiply Signed R1:R0<–RdxRr Z,C 2
mulsu Rd, Rr Multiply Signed with Unsigned R1:R0<–RdxRr Z,C 2
fmul Rd, Rr Fractional Multiply Unsigned R1:R0<–
(RdxRr)»1
Z,C 2
fmuls Rd, Rr Fractional Multiply Signed R1:R0<–
(RdxRr)»1
Z,C 2
fmulsu Rd, Rr Fractional Multiply Signed with Un-
signed
R1:RCX–
(RdxRr)»1
Z,C 2
