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Ȼɢɬɨɜɵɟ ɤɨɦɚɧɞɵ ɦɢɤɪɨɤɨɧɬɪɨɥɥɟɪɚ ȺɌɬɟgɚ163
Ɇɧɟɦɨ-
ɧɢɤɚ
Ɉɩɟɪɚɧɞɵ Ɉɩɢɫɚɧɢɟ Ɉɩɟɪɚɰɢɹ Ɏɥɚɝɢ Ɍɚɤɬ
sbi P*,b Set Bit in I/O Re
g
ister I/O
(
P,b
)
<–1 None 2
cbi P*,b Clear Bit in
I/O Register
I/O(P,b) <– 0 None 2
lsl Rd Logical Shift Left Rd(n+1) <– Rd(n), Rd(0) <– 0 Z,C,N,V 1
lsr Rd Logical Shift Right Rd(n)<–Rd(n+1), Rd(7)<–0 Z,C,N,V 1
rol Rd Rotate Left
Through Carry
Rd(0)<–C, Rd(n+1)<– Rd(n),
C <– Rd(7)
Z,C,N,V 1
rɨɝ Rd Rotate Right
Through Carry
Rd(7) <– C,Rd(n)<–
Rd(n+1),C<–Rd(0)
Z,C,N,V 1
rsr Rd Arithmetic Shift Right Rd(n)<–Rd(n+1), n=0..6 Z,C,N,V 1
swap Rd Swap Nibbles Rd(3..0)<–Rd(7..4),
Rd(7..4) <–Rd(3..0)
None 1
bset s Flag Set SREG(s) <–1 SREG(s) 1
bclr s Flag Clear SREG(s) <– 0 SREG(s) 1
bld Rd, b Bit load from T
to Re
g
ister
Rd(b) <– T None 1
bst Rr, b Bit Store from Register
to T
T <– Rr(b) T 1
sec Set Carry C<–1 ɋ 1
clc Clear Carry C<–0 ɫ 1
sen Set Negative Flag N<–1 N 1
cln Clear Negative Flag N<–0 N 1
sez zSet Zero Flag Z <–1 z 1
clz Clear Zero Fla
g
Z<–0 z 1
sei Global Interrupt Enable K–1 I 1
cli Global Interrupt
Di
s
a
b
l
e
<–0 I 1
ses Set Signed Test Flag S<–1 s 1
cls Clear Signed Test Flag S<–0 s 1
sev Set Twos
Complement Overflow
V<–1 V 1
clv Clear Twos
Complement Overflow
V<–0 V 1
set SetTinSREG T<–1 T 1
clt Clear T in SREG T<–0 T 1
she Set Half Carry Flag
in SREG
H<–1 H 1
clh Clear Half Carry Flag in
SREG
H<–0 H 1
96
Ʉɨɦɚɧɞɵ ɩɟɪɟɯɨɞɨɜ ɦɢɤɪɨɤɨɧɬɪɨɥɥɟɪɚ ȺɌɬɟgɚ163
Ɇɧɟɦɨ-
ɧɢɤɚ
Ɉɩɟɪɚɧɞɵ Ɉɩɢɫɚɧɢɟ Ɉɩɟɪɚɰɢɹ Ɏɥɚɝɢ Ɍɚɤɬ
rjmp k Relative Jump PC <– PC + k + 1 None 2
ijmp Indirect Jump to (Z) PC<–Z None 2
jmp k Jump PC<–k None 3
rcall k Relative Subroutine Call PC <– PC + k + 1 None 3
call k Call Subroutine PC<–k None 4
icall Indirect Call to (Z) PC<–Z None 3
ret Subroutine Return PC <– STACK None 4
reti Interrupt Return PC <– STACK I 4
cpse Rd,Rr Compare, Skip if Equal
if (Rd = Rr) PC <– PC +
2 or3
None 1/2/ 3
sbrc Rr, b
Skip if Bit in Regis-
ter Cleared
if(Rr(b)=0) PC<–PC + 2 or3 None 1/2
sbrs Rr, b Skip if Bit in Register is Set if (Rr(b)=1)PC<–PC + 2 or3 None 1/2
sbic P*, b
Skip if Bit in I/O Register
Cleared
if (P(b)=0) PC <– PC + 2
or 3
None 1/2
sbis P*, b
Skip if Bit in I/O Register is
Set
if(P(b)=1)PC<–PC + 2or 3 None 1/2
brbs s, k Branch if Status Flag Set
if(SREG(s)=1)thenPC <–
PC+k + 1
None 1/2
brbc s, k Branch f Status Flag Cleared
if(SREG(s) = 0) then PC <–
PC+k + 1
None 1/2
breq k Branch if Equal if(Z=1)thenPC<–PC + k+1 None 1/2
brcs k Branch if Carry Set if(C=1)thenPC<–PC + k+ 1 None 1/2
brne k Branch if Not Equal
if (Z = 0) then PC <– PC
+ k+1
None 1/2
brcc k Branch if Carry Cleared
if (C = 0) then PC <– PC
+ k+ 1
None 1/2
brsh k Branch if Same or Higher
if (C = 0) then PC <– PC
+ k+ 1
None 1/2
brlo k Branch if Lower if(C=1)thenPC<–PC + k+1 None 1/2
brmi k Branch if Minus
if (N = 1)thenPC<–PC + k+
1
None 1/2
