Операционное устройство. Хлуденев А.В. - 45 стр.

                VHDL-модель управляющего автомата Мура

     -- Moore State machines
     library ieee;
     use ieee.std_logic_1164.all;
     use ieee.numeric_std.all;

     entity UA is
      port(
         x1, x2 : in std_logic;
            ck, reset : in std_logic;
         y1, y2, y3, y4 : out std_logic );
     end UA;

     architecture behavior of UA is
      type state_type is (s0, s1, s2, s3, s4);
      signal current_state, next_state : state_type;
     begin
      -- register block
      process (ck, reset)
      begin
         if reset = '1' then
           current_state <= s0;
         elsif ck = '1' and ck'event then
           current_state <= next_state;
         end if;
      end process;

      -- state machine process
      process (current_state, x1, x2)
      begin
       -- default outputs
       y1 <= '0';
       y2 <= '0';
       y3 <= '0';
       y4 <= '0';

     case current_state is

        when s0 =>
          next_state <= s1;

        when s1 =>
          y1 <= '1';
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