Проектирование цифровых устройств с помощью языка описания аппаратуры VHDL. Бобрешов А.М - 12 стр.

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12
Пример 5. Мультиплексор 4:1
library IEEE;
use IEEE.std_logic_1164.all;
entity MUX is
port(C,D,E,F: in std_logic;
S: in std_logic_vector(1 downto 0);
MUX_OUT: out std_logic);
end MUX;
architecture MUX_ARCH of MUX is
begin
process(S,C,D,E,F)
begin
case S is
when “00” => MUX_OUT <=C;
when “01” => MUX_OUT <=D;
when “10” => MUX_OUT <=E;
when others => MUX_OUT <=F;
end case;
end process;
end MUX_ARCH;
Пример 6. Дешифратор
library IEEE;
use IEEE.std_logic_1164.all;
entity DECODE is
port (AIN: in std_logic_vector(1 downto 0);
EN: in std_logic;
YOUT: out std_logic_vector(3 downto 0));
end DECODE;
architecture DECODE _ARCH of DECODE is
begin
process (AIN, EN)
begin
if EN=’0’ then YOUT<=(others=>’0’);
else
case AIN is
when “00” => YOUT <= “0001”;
when “01” => YOUT <= “0010”;
when “10” => YOUT <= “0100”;
when “11” => YOUT <= “1000”;
C
D
E
F
MUX OUT
S
(
1:0
)
MUX
DC
YOUT
(
3
)
YOUT
(
2
)
YOUT
(
1
)
YOUT
(
0
)
AIN
(
1
)
AIN
(
0
)
                                            12


                           Пример 5. Мультиплексор 4:1

library IEEE;
use IEEE.std_logic_1164.all;

entity MUX is
  port(C,D,E,F: in std_logic;
  S: in std_logic_vector(1 downto 0);
  MUX_OUT: out std_logic);
end MUX;

architecture MUX_ARCH of MUX is
  begin
    process(S,C,D,E,F)
     begin
       case S is                                     C
         when “00” =>    MUX_OUT <=C;                D
                                                          MUX      MUX OUT
         when “01” =>    MUX_OUT <=D;                E
         when “10” =>    MUX_OUT <=E;
                                                     F
         when others =>  MUX_OUT <=F;
      end case;
                                                          S(1:0)
   end process;
end MUX_ARCH;

                               Пример 6. Дешифратор

library IEEE;
use IEEE.std_logic_1164.all;

entity DECODE is
  port (AIN: in std_logic_vector(1 downto 0);
  EN: in std_logic;
  YOUT: out std_logic_vector(3 downto 0));
end DECODE;                                                 DC       YOUT(3)
                                                 AIN(1)              YOUT(2)
architecture DECODE _ARCH of DECODE is           AIN(0)              YOUT(1)
  begin                                                              YOUT(0)
    process (AIN, EN)
      begin
        if EN=’0’ then YOUT<=(others=>’0’);
        else
           case AIN is
             when “00” => YOUT <= “0001”;
             when “01” => YOUT <= “0010”;
             when “10” => YOUT <= “0100”;
             when “11” => YOUT <= “1000”;

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