Организация вычислительных систем и сетей. Халабия Р.Ф. - 45 стр.

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Структурная схема микропроцессора Pentium
a b
256
e d c
g
a
e g
e
a
32
32 32
Рис. 4.8.
Control Unit
DP
Logic
Branch
Target
Buffer
Code Cache
8 KBytes
TLB
Control
ROM
Prefetch Buffers
Instruction Decode
Bus
Unit
Page
Unit
Address
Generate
U pipeline
Address
Generate
V pipeline
Integer Register File
ALU
U Pipeline
ALU
V Pipeline
Barrel
Shiffer
APIC
Data Cache
8 KBytes
TLB
Floating Point Unit
80 80
Control
Register File
ADD
Divide
Multiply
a - Control
b - Prefetch Address
c - Inctruction Pointer
d - Branch Verification &
Target Address
e - 64-bit Data Bus
g - 32-bit Address Bus 
                                             Структурная схема микропроцессора Pentium

                                                  TLB        Code Cache                                             a - Control
a                               Branch       b               8 KBytes                                               b - Prefetch Address
      DP
                                Target                                                                              c - Inctruction Pointer
     Logic
                                Buffer                                256                                           d - Branch Verification &
                                                                                                                    Target Address
                                                       Prefetch Buffers                                             e - 64-bit Data Bus
       e                    d            c                                                      Control
                                                                                                                    g - 32-bit Address Bus
     Bus                                                                                         ROM
     Unit                                             Instruction Decode

      g
                                                                 Control Unit
       a
                                                                                                           Floating Point Unit
                     Page                                Address             Address
                     Unit                               Generate            Generate                             Control
                                                        U pipeline          V pipeline
                                                                                                               Register File

                                                             Integer Register File
                                                                                                                  ADD
             e   g
                                                             ALU                ALU
                                                           U Pipeline         V Pipeline
                                                                                                                  Divide
      e                                                     Barrel
    APIC
                                                            Shiffer
      a                                                                                                          Multiply

                                                                                                          80                   80
                                                      32
                                                                         Data Cache
                                                               TLB       8 KBytes
                                                 32                                        32


                                                                        Рис. 4.8.


                                                                        45

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