Применение языка VHDL при проектировании специализированных СБИС. Ивченко В.Г. - 44 стр.

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component adder

port (a : in bit_vector (31 downto 0);

b : in bit_vector (31 downto 0);

res : out bit_vector (31 downto 0));

end component;

component and_32

port (a : in bit_vector (31 downto 0);

cmd : in bit;

res : out bit_vector (31 downto 0));

end component;

component falling_edge_reg

port (din : in bit_vector (31 downto 0);

clk : in bit;

dout : out bit_vector (31 downto 0));

end component;

begin

my_adder : adder

port map (a => eff_data, b => accu_out, res => adder_out);

my_mux : and_32

port map (cmd => command, a => accu_out, res => eff_data);

my_reg : falling_edge_reg

port map (din => adder_out, clk => clk, dout => accu_out);

end;