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Library ieee;
Use ieee.std_logic_1164.all;
Entity T is
Port ( c: in std_logic;
q: out std_logic);
end T;
architecture beh of T is
Signal d: std_logic :=’0’;
Begin
Process (c)
Begin
if c=’0’ and c’event then
d<= not d; q<=d;
End if;
End process;
End beh;
