Математическое моделирование в микроэлектронике. Ч.2. Лукьяненко Е.Б. - 20 стр.

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20
X0, X1, X2, X3: in std_logic;
F: out std_logic);
Architecture behavior of mux is
Begin
Process (A, X0, X1, X2, X3)
Begin
If A=”00” then F<=X0;
Elsif A=”01” then F<=X1;
Elsif A=”11” then F<=X2;
Elsif A=”11” then F<=X3;
End if;
End process;
End behavior;
Другая форма записи:
Lidrary ieee;
Use ieee.std_logic_1164.all;
Entity mux is
Port (A: in std_logic_vector (1 downto 0);
X0, X1, X2, X3: in std_logic;
F: out std_logic);
Architecture behavior of mux is
Begin
Process (A, X0, X1, X2, X3)
Begin
Case A is
When “00” => F<=X0;
When “01” => F<=X1;
When “10” => F<=X2;
When “11” => F<=X3;
End case;
End process;
End behavior;

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