Проектирование цифровых устройств с помощью языка описания аппаратуры VHDL. Бобрешов А.М - 49 стр.

                                             49
  DATA_READY                : in std_logic;
  CLK              : in std_logic;     --bitrate x 16 clock;
  BUSY                      : out std_logic;
  TxD                       : out std_logic);
end RS232_TX;

architecture RS232_TX_ARCH of RS232_TX is
type STATES is (WAIT_FOR_BYTE, BYTE_TRANSFER);
signal STATE: STATES:=WAIT_FOR_BYTE;
signal REG: std_logic_vector(9 downto 0);
signal TICK: integer range 0 to 255:=0;
  begin
    TxD<=REG(0);
    BUSY<='0' when state=WAIT_FOR_BYTE else '1';

  process(RST,CLK)
    begin
      if RST='1' then STATE<=WAIT_FOR_BYTE;
        elsif CLK'event and CLK='1' then
               case (STATE) is
                 when WAIT_FOR_BYTE =>
                   if DATA_READY='1' then STATE<=BYTE_TRANSFER;
                   else null;
                   end if;
                when BYTE_TRANSFER =>
                 if TICK=160 then
                    STATE<=WAIT_FOR_BYTE;
                 else null;
                 end if;
               end case;
       end if;
      end process;

 process(RST, STATE, CLK)
   begin
       if RST='1' or STATE= WAIT_FOR_BYTE then TICK<=0;
       elsif CLK'event and CLK='1' then TICK<=TICK+1;
       end if;
  end process;

 process (RST, CLK)
   begin
       if RST='1' then REG<=(others=>'1');
       elsif CLK'event and CLK='1' then
          if state=WAIT_FOR_BYTE then REG<=DATA&"01";
          elsif (TICK=1 or TICK=17 or TICK=33 or TICK=49 or TICK=65 //
           or TICK=81 or TICK=97 or TICK=113 or TICK=129 or TICK=145)
          then REG(9 downto 0) <= '1' & REG(9 downto 1);
          else null;
          end if;